Patents
Inventing for over 25 years. Our patents prove it.
Year after year our patent list grows a little longer, deepening and widening our IP portfolio. Each patent is a testament to our innovation and further validation of our technology leadership in the industry.
The following is a summary of patents held by ANADIGICS.
Further details on these patents can be obtained from the following site:
US Patent and Trademark Office
Patent No. 8130043: Multi-stage power amplifier with enhanced efficiency
Patent No. 7890288: Timing functions to optimize code-execution time
Patent No. 7890065: Temperature compensated power detector
Patent No. 7852172: High-power switch
Patent No. 7830456: System and method for frequency multiplexing in double-conversion receivers
Patent No. 7764942: Tuning circuitry utilizing frequency translation of an impedance from a fixed-filter frequency response
Patent No. 7718486: Structures and methods for fabricating vertically integrated HBT-FET device
Patent No. 7639069: Tunable balanced loss compensation in an electronic filter
Patent No. 7586720: Electrostatic discharge protection device
Patent No. 7564230: Voltage regulated power supply system
Patent No. 7545218: Device and method for power amplifier noise reduction
Patent No. 7545217: System and method for improving power efficiency in GSM power amplifiers
Patent No. 7459974: System and method for distortion cancellation in amplifiers
Patent No. 7443236: CDMA power amplifier design for low and high power modes
Patent No. 7400873: Method and system for image rejection by using post mixer I/Q
Patent No. 7385447: Power amplifier having curve-fitting predistorter
Patent No. 7348852: Device and method for power amplifier noise reduction
Patent No. 7301396: System and method for distortion cancellation in amplifiers
Patent No. 7292104: Variable gain amplifier
Patent No. 7248111: Multi-mode digital bias control for enhancing power amplifier efficiency
Patent No. 7202736: CDMA power amplifier design for low and high power modes
Patent No. 7173406: Method and apparatus for gain control
Patent No. 7102444: Method and apparatus for compensating and improving efficiency in a variable power amplifier
Patent No. 7071514: Electrostatic discharge protection device
Patent No. 7019508: Temperature compensated bias network
Patent No. 7015519: Structures and methods for fabricating vertically integrated HBT/FET device
Patent No. 7009454: Method and apparatus for optimization of amplifier with adjustable output range
Patent No. 6998920: Monolithically Fabricated HBT Amplification Stage with Current Limiting FET
Patent No. 6970039: Efficiency enhancement for MMIC amplifiers
Patent No. 6937102: Low bias current/temperature compensation current mirror for linear power amplifier
Patent No. 6882227: Bias Circuit Linearization and Dynamic Power Control
Patent No. 6856004: Compact layout for a semiconductor device
Patent No. 6853526: Transient Overvoltage Protection Circuit
Patent No. 6842075: Gain Block with Stable Internal Bias from Low-voltage Power Supply
Patent No. 6806767: Power Amplifier with Load Switching Circuit
Patent No. 6803824: Dynamic Matching in Cascode Circuits
Patent No. 6760900: Integrated circuits with scalable design
Patent No. 6759922: High directivity multi-band coupled-line coupler for RF power amplifier
Patent No. 6753734: Multi-mode amplifier bias circuit
Patent No. 6724067: Low stress thermal and electrical interconnects for heterojunction bipolar transistors
Patent No. 6719518: Portable tube holder apparatus
Patent No. 6710657: Gain control circuit with well-defined gain states
Patent No. 6664500: Laser-trimmable digital resistor
Patent No. 6645790: System and Method for Prototyping and Fabricating Complex Microwave Circuits
Patent No. 6642578: Improved Linearity Radio Frequency Switch with Low Control Voltage
Patent No. 6639466: Amplifier bias adjustment circuit to maintain high-output third-order intermodulation distortion performance
Patent No. 6580321: Active clamping circuit for power amplifier
Patent No. 6577198: Active power splitter with impedance matching
Patent No. 6559722: Low bias current/temperature compensation current mirror for linear power amplifier
Patent No. 6554949: Wafer demount receptable for separation of thinned wafer from mounting carrier
Patent No. 6515546: Bias circuit for use with low-voltage power supply
Patent No. 6501331: Multi-band amplifier
Patent No. 6491083: Wafer demount receptacle for separation of thinned wafer from mounting carrier
Patent No. 6470946: Wafer demount gas distribution tool
Patent No. 6458640: GaAs MESFET having LDD and non-uniform P-well doping profiles
Patent No. 6437585: Electrical contactor for automatic testing of chips including RF chips
Patent No. 6415843: Spatula for separation of thinned wafer from mounting carrier
Patent No. 6404284: Amplifier bias adjustment circuit to maintain high-output third-order intermodulation distortion performance
Patent No. 6314008: Adjustable low spurious signal DC-DC converter
Patent No. 6242986: Multiple-band amplifier
Patent No. 6005375: Amplifier using a single polarity power supply
Patent No. 5952860: Amplifier using a single polarity power supply
Patent No. 5892400: Amplifier using a single polarity power supply
Patent No. 5774017: Multiple-band amplifier
Patent No. 5748049: Multi-frequency local oscillators
Patent No. 5736913: Method and apparatus for providing grounding to microwave circuit by low impedance means
Patent No. 5659894: Dual-channel low current low noise block downconverter
Patent No. 5646573: Automatic gain-control transimpedance amplifier
Patent No. 5625307: Low cost monolithic gallium arsenide upconverter chip
Patent No. 5602510: Automatic transimpedance control amplifier variable impedance feedback
Patent No. 5563545: Low cost monolithic GaAs upconverter chip
Patent No. 5557144: Plastic packages for microwave frequency applications
Patent No. 5493718: Dual-channel low current low noise block downconverter
Patent No. 5442321: Automatic transimpedance control amplifier
Patent No. 5428837: Method and apparatus for reducing local oscillator leakage in IC receivers
Patent No. 8130043: Multi-stage power amplifier with enhanced efficiency
ISSUED: March 6, 2012
FILED: February 13, 2007
APPLICATION NUMBER: 11/706,060
ABSTRACT:
A multi-stage RF/Microwave power amplifier circuit is provided that is capable of operating efficiently at multiple output power levels. The amplifier comprises first and second amplifying stages, an output impedance matching network connected to the output of first amplifying stage and an interstage impedance matching network connected between the outputs of said first and second amplifying stages. In a high power mode, the first amplifying stage is enabled and the second amplifying stage is disabled and the output and interstage impedance matching networks present a first value of the output impedance that improves the efficiency of the first amplifying stage. In a low power mode, the first amplifying stage is disabled and the second amplifying stage is enabled, and output and interstage impedance matching networks present a second value of the output impedance that improves the efficiency of the second amplifying stage.
Patent No. 7890288: Timing functions to optimize code-execution time
ISSUED: February 15, 2011
FILED: November 5, 2007
APPLICATION NUMBER: 11/982,786
ABSTRACT:
A method and system for optimizing a test plan of an Integrated Circuit (IC). The test plan includes two or more test sequences. A test sequence includes the measurement of a parameter of the IC. The total test time of the IC is reduced by performing one or more activities during a desired wait time associated with the measurement of the parameter. The test plan may be further optimized by modifying the one or more activities performed during the desired wait time.
Patent No. 7890065: Temperature compensated power detector
ISSUED: February 15, 2011
FILED: September 1, 2006
APPLICATION NUMBER: 11/515,260
ABSTRACT:
A temperature-compensated power detector for detecting variations in the power level of an RF signal. The temperature-compensated power detector includes a detector circuit and a temperature compensating circuit. The detector circuit detects the power level of an RF signal and provides an output voltage that corresponds to the power level of the RF signal. The temperature compensating circuit ensures that the output voltage of the temperature-compensated power detector is independent of changes in the temperature.
Patent No. 7852172: High-power switch
ISSUED: December 14, 2010
FILED: July 18, 2008
APPLICATION NUMBER: 12/218,912
ABSTRACT:
A low-loss Radio Frequency (RF) switch for high-power RF signals. The RF switch includes a first-biasing circuit connected to a first transistor and a second-biasing circuit connected to a second transistor. The RF switch switches its output signal between a first input signal and a second input signal. The first transistor is in a conduction state and the second transistor is in a non-conduction state when the first input signal is to be conducted to the output signal. The first-biasing circuit biases the first transistor at a first voltage for increasing conduction of the first input signal and the second-biasing circuit biases the second transistor at a second voltage for decreasing conduction of the first input signal. Moreover, the second transistor is in a conduction state and the first transistor is in a non-conduction state when the second input signal is to be conducted to the output signal.
Patent No. 7830456: System and method for frequency multiplexing in double-conversion receivers
ISSUED: November 9, 2010
FILED: June 2, 2006
APPLICATION NUMBER: 11/446,337
ABSTRACT:
A system and method for frequency conversion in a frequency-conversion receiver is disclosed. The frequency-conversion receiver receives input RF signals carrying multiple channels. The frequency-conversion receiver converts the input RF signals to a wide IF band. The IF band is further processed by dividing the IF band into one or more frequency segments or by selecting a wideband frequency segment from the IF band. The wideband frequency segment or the one or more frequency segments are further down-converted, filtered and amplified to provide desired output IF signals, based on the number of channels required in the output IF signals.
Patent No. 7764942: Tuning circuitry utilizing frequency translation of an impedance from a fixed-filter frequency response
ISSUED: July 27, 2010
FILED: July 6, 2007
APPLICATION NUMBER: 11/825,414
ABSTRACT:
A circuit and method for tracking a local oscillator signal frequency in an RF tuner, for tuning input RF signals. The RF tuner includes a frequency-dependent impedance generator that generates a frequency-dependent impedance at the input by rejecting unwanted input RF signals and shunt feeding back the desired signal to the input. The desired signal frequency is centered at the local oscillator signal frequency. The frequency-dependent impedance generator is used with an amplifier circuit to generate a tracking amplifier, the frequency-dependent amplifier gain of which tracks the local oscillator signal frequency.
Patent No. 7718486: Structures and methods for fabricating vertically integrated HBT-FET device
ISSUED: May 18, 2010
FILED: January 13, 2006
APPLICATION NUMBER: 11/331,630
ABSTRACT:
Methods and systems for fabricating integrated pairs of HBT/FET's are disclosed. One preferred embodiment comprises a method of fabricating an integrated pair of GaAs-based HBT and FET. The method comprises the steps of: growing a first set of epitaxial layers for fabricating the FET on a semi-insulating GaAs substrate; fabricating a highly doped thick GaAs layer serving as the cap layer for the FET and the subcollector layer for the HBT; and producing a second set of epitaxial layers for fabricating the HBT.
Patent No. 7639069: Tunable balanced loss compensation in an electronic filter
ISSUED: December 29, 2009
FILED: May 8, 2008
APPLICATION NUMBER: 12/151,699
ABSTRACT:
The invention provides a system for providing tunable balanced loss compensation in an electronic filter. Tunable balanced loss compensation is provided by using cross-connected balanced transconductors and self-connected balanced transconductors. The cross-connected balanced transconductors and the self-connected transconductors compensate the unbalanced loss across the electronic filter. The self-connected balanced transconductors compensate the balanced loss across the electronic filter. Further, the cross-connected and the self-connected balanced transconductors are tunable by adjusting the values of their transconductances, thereby providing tunable balanced loss compensation.
Patent No. 7586720: Electrostatic discharge protection device
ISSUED: September 8, 2009
FILED: December 2, 2004
APPLICATION NUMBER: 11/002,345
ABSTRACT:
A compact ESD protection device is described that uses the reverse breakdown voltage of a base-emitter junction as a trigger diode to switch a transistor that shunts the forward bias ESD current to ground. The trigger diode in series with a leakage diode provides a path to shunt the reverse bias ESD current to ground. The leakage diode is matched to the trigger diode to shunt any leakage current from the trigger diode to ground.
Patent No. 7564230: Voltage regulated power supply system
ISSUED: July 21, 2009
FILED: January 11, 2006
APPLICATION NUMBER: 11/329,449
ABSTRACT:
A voltage regulator for providing a regulated voltage is disclosed. The voltage regulator comprises an error amplifying module and a regulator. The error amplifying module provides a reference voltage, based on an output voltage to be regulated. The regulator provides a regulated output voltage based on the reference voltage. Voltage regulator provides stable output voltage against variations caused by power supply and load with a defined temperature coefficient.
Patent No. 7545218: Device and method for power amplifier noise reduction
ISSUED: June 9, 2009
FILED: March 24, 2008
APPLICATION NUMBER: 12/054058
ABSTRACT:
A power amplifier for use in wireless communication devices is disclosed that reduces the noise generated at the output of the amplifier in the receive band of the wireless communication device. A resonant circuit is inserted between the base ballast resister and the lumped resister. The resonant frequency of the resonant circuit is adjusted to correspond to the frequency offset between the transmission frequency and the frequency corresponding to the peak noise in the receive band of the communication device.
Patent No. 7545217: System and method for improving power efficiency in GSM power amplifiers
ISSUED: June 9, 2009
FILED: May 12, 2004
APPLICATION NUMBER: 10/844,649
ABSTRACT:
A method and circuit system for improving power efficiency of RF power amplifiers is disclosed. A preferred embodiment comprises a power amplifier comprising: a plurality of amplifier stages, a power regulator providing an output supply voltage at an output node responsive to an adjustable power control signal, wherein the output supply voltage is applied to at least one stage of a power amplifier; and an amplifier biaser providing a bias signal corresponding to the adjustable power control signal, wherein the output supply voltage and the bias signal are independently generated as functions of the adjustable power control signal.
Patent No. 7459974: System and method for distortion cancellation in amplifiers
ISSUED: December 2, 2008
FILED: November 27, 2007
APPLICATION NUMBER: 11/945,800
ABSTRACT:
A distortion cancellation amplifier is described having a main amplifier and an error amplifier. The main amplifier, in response to an input signal, generates an output signal having an amplified signal component and a distortion signal component. The error amplifier is sized and biased to generate, in response to the same input signal, a distortion signal component that has substantially the same magnitude as the distortion signal component of the main amplifier. The distortion signal component from the error amplifier is subtracted from the output signal of the main amplifier.
Patent No. 7443236: CDMA power amplifier design for low and high power modes
ISSUED: October 28, 2008
FILED: April 6, 2007
APPLICATION NUMBER: 11/784,541
ABSTRACT:
An amplifier circuit responsive to a power mode signal improves efficiency at low power levels without compromising efficiency at high power levels. At low power levels, high impedance is presented with suitable adjustment in the phase of the signal. Also, providing for predistortion linearization improves high power efficiency and switching the predistortion linearizer OFF at low power levels contributes little more than a small insertion loss. The power amplifier also uses a bias circuit incorporating a dual harmonic resonance filter to provide high impedance at a fundamental frequency and low impedance at a second harmonic. These properties are of particularly advantageous since amplifiers in cell-phones are used in low power modes most of the time although they are designed to be most efficient at primarily the highest power levels.
Patent No. 7400873: Method and system for image rejection by using post mixer I/Q equalization
ISSUED: July 15, 2008
FILED: October 20, 2005
APPLICATION NUMBER: 11/254,386
ABSTRACT:
The invention provides a system and method for tuning broadband signals by using post mixer I/Q equalization. An Image Rejection Mixer (IRM) is used for mixing Radio Frequency (RF) signals and rejecting image signals from the desired RF signals. The IRM includes an I/Q mixer and a filter. The I and Q paths resulting from the mixing operation in the I/Q mixer are equalized in amplitude and phase by an I/Q equalizer. Thereafter, the image signals are rejected from the desired RF signals using the filter.
Patent No. 7385447: Power amplifier having curve-fitting predistorter
ISSUED: June 10, 2008
FILED: June 28, 2004
APPLICATION NUMBER: 10/879,940
ABSTRACT:
A power amplifier has a plurality of amplifier stages. One or more predistorters are each placed between amplifier stages within the power amplifier path. The predistorters set breakpoints in a predistortion curve and divide the predistortion curve into a plurality of segments. Each predistorter may be adjusted to change the slope of each segment. This adjustment forms a piecewise curve-fit to approximate the inverse of the amplifier transfer characteristic. The curve-fit can be made arbitrarily close to the amplifier transfer characteristic by the selection of a sufficient number of breakpoints and therefore a sufficient number of predistortion curve segments, leading to a satisfactory linearization of the power amplifier.
Patent No. 7348852: Device and method for power amplifier noise reduction ISSUED: March 25, 2008
FILED: November 8, 2004
APPLICATION NUMBER: 10/984,316
ABSTRACT:
A power amplifier for use in wireless communication devices is disclosed that reduces the noise generated at the output of the amplifier in the receive band of the wireless communication device. A resonant circuit is inserted between the base ballast resister and the lumped resister. The resonant frequency of the resonant circuit is adjusted to correspond to the frequency offset between the transmission frequency and the frequency corresponding to the peak noise in the receive band of the communication device.
Patent No. 7301396: System and method for distortion cancellation in amplifiers
ISSUED: November 27, 2007
FILED: December 16, 2004
APPLICATION NUMBER: 11/015,863
ABSTRACT:
A distortion cancellation amplifier is described having a main amplifier and an error amplifier. The main amplifier, in response to an input signal, generates an output signal having an amplified signal component and a distortion signal component. The error amplifier is sized and biased to generate, in response to the same input signal, a distortion signal component that has substantially the same magnitude as the distortion signal component of the main amplifier. The distortion signal component from the error amplifier is subtracted from the output signal of the main amplifier.
Patent No. 7292104: Variable gain amplifier
ISSUED: November 6, 2007
FILED: February 11, 2005
APPLICATION NUMBER: 11/057,304
ABSTRACT:
A variable gain amplifier is disclosed where the gain of the amplifier is controlled by a variable emitter resistor that is responsive to a control signal. The variable resistor includes a resistor connected between the collector and emitter of a control transistor. A control signal applied to the base of the control transistor varies the gain of the amplifier from a minimum gain when the control transistor is cut-off to a maximum gain when the control transistor is saturated.
Patent No. 7248111: Multi-mode digital bias control for enhancing power amplifier efficiency
ISSUED: July 24, 2007
FILED: April 14, 2005
APPLICATION NUMBER: 11/106,254
ABSTRACT:
A power amplifier with a multi-mode digital bias control circuit is provided. The power amplifier utilizes a complementary reference voltage generation circuit and a bias current-control circuit to generate a plurality of bias current levels for different output power levels. In an embodiment of the present invention, the power amplifier circuit is connected to a reference voltage and two control signals. Depending on the desired output power level, the control signals set the corresponding bias current in the amplifying transistors, to ensure sufficient linearity. The power amplifier is capable of operating at a very low quiescent current level, for example, 5 mA. As a result, a significant improvement in the power amplifier's overall efficiency is achieved, and the battery talk time of a wireless communication device is increased. The invention finds application in wireless communication devices such as CDMA, WCDMA, EDGE and WLAN mobile devices.
Patent No. 7202736: CDMA power amplifier design for low and high power modes
ISSUED: April 10, 2007
FILED: March 23, 2004
APPLICATION NUMBER: 10/807,764
ABSTRACT:
An amplifier circuit responsive to a power mode signal improves efficiency at low power levels without compromising efficiency at high power levels. At low power levels, high impedance is presented with suitable adjustment in the phase of the signal. Also, providing for predistortion linearization improves high power efficiency and switching the predistortion linearizer OFF at low power levels contributes little more than a small insertion loss. The power amplifier also uses a bias circuit incorporating a dual harmonic resonance filter to provide high impedance at a fundamental frequency and low impedance at a second harmonic. These properties are of particularly advantageous since amplifiers in cell-phones are used in low power modes most of the time although they are designed to be most efficient at primarily the highest power levels.
Patent No. 7173406: Method and apparatus for gain control
ISSUED: February 6, 2007
FILED: August 26, 2004
APPLICATION NUMBER: 10/927,363
ABSTRACT:
A method and apparatus for power amplifier gain control is provided, such as may be embodied as an integrated circuit is disclosed. Embodiments provide for a continuously variable gain control at low cost as contrasted two-state or multi-state capabilities of previously developed solutions.Improved consistency and control over gain may be provided using features disclosed.
Patent No. 7102444: Method and apparatus for compensating and improving efficiency in a variable power amplifier
ISSUED: September 5, 2006
FILED: September 24, 2004
APPLICATION NUMBER: 10/949,087
ABSTRACT:
A method and apparatus for an amplifier, such as a radio frequency amplifier embodiment as an integrated circuit is disclosed. Embodiments provide for operating with good energy efficiency at multiple power levels. Resonant components act to provide consistent operating parameters over the wide range of power levels used. A compensating impedance is switched into or out of circuit in high power mode to improve the match that would pertain without the compensation. Improved compensation and linearity may be provided using features disclosed. The invention may operate in the microwave region or at other RFs.
Patent No. 7071514: Electrostatic discharge protection device
ISSUED: July 4, 2006
FILED: December 2, 2004
APPLICATION NUMBER: 002302
ABSTRACT:
A compact ESD protection device is described that uses the reverse breakdown voltage of a base-emitter junction as a trigger diode to switch a transistor that shunts the forward bias ESD current to ground. The trigger diode in series with a leakage diode provides a path to shunt the reverse bias ESD current to ground. The leakage diode is matched to the trigger diode to shunt any leakage current from the trigger diode to ground.
Patent No. 7019508: Temperature compensated bias network
ISSUED: March 28, 2006
FILED: June 24, 2004
APPLICATION NUMBER: 875819
ABSTRACT:
A method and apparatus for a temperature compensated bias network, such as may be embodied as an integrated circuit is disclosed. Embodiments provide for a wide range of desired temperature characteristics with good stability. Current mirror components with active leakage circuits may act to provide consistent operating parameters over a wide range of temperatures. Improved compensation and linearity may be provided using features disclosed.
Patent No. 7015519: Structures and methods for fabricating vertically integrated HBT/FET device
ISSUED: March 21, 2006
FILED: February 20, 2004
APPLICATION NUMBER: 783830
ABSTRACT:
Methods and systems for fabricating integrated pairs of HBT/FET's are disclosed. One preferred embodiment comprises a method of fabricating an integrated pair of GaAs-based HBT and FET. The method comprises the steps of: growing a first set of epitaxial layers for fabricating the FET on a semi-insulating GaAs substrate; fabricating a highly doped thick GaAs layer serving as the cap layer for the FET and the subcollector layer for the HBT; and producing a second set of epitaxial layers for fabricating the HBT.
Patent No. 7009454: Method and apparatus for optimization of amplifier with adjustable output range
ISSUED: March 7, 2006
FILED: January 20, 2004
APPLICATION NUMBER: 760698
ABSTRACT:
A method and apparatus for an amplifier, such as a radio frequency amplifier embodied as an integrated circuit is disclosed. Embodiments provide for a wide range of operating powers with good energy efficiency at many power levels. Resonant components act to provide consistent operating parameters over the wide range of power levels used. The invention may operate in the microwave region or at other RFs.
Patent No. 6998920: Monolithically Fabricated HBT Amplification Stage with Current Limiting FET
ISSUED: February 14, 2006
FILED: February 20, 2004
APPLICATION NUMBER: 783825
ABSTRACT:
A monolithically integrated amplifier comprising at least one heterojunction bipolar transistor and at least one field effect transistor is disclosed wherein the field effect transistor provides improved ruggedness by limiting the base and/or collector current to the HBT during severe load mismatch and/or high overdrive.
Patent No. 6970039: Efficiency enhancement for MMIC amplifiers
ISSUED: November 29, 2005
FILED: October 23, 2003
APPLICATION NUMBER: 692232
ABSTRACT:
The present innovation is directed to a single-chip integrated circuit power amplifier configured to employ the efficiency enhancement techniques utilized in Doherty amplifiers. The single-chip integrated circuit power amplifier may be implemented using uniquely designed biasing circuits as described herein. Also, the use of combined HBT/FET processes and a lumped quarter-wavelength transformer may be inherently well suited for the implementation of Doherty amplifiers in the single-chip techniques described herein.
Patent No. 6937102: Low bias current/temperature compensation current mirror for linear power amplifier
ISSUED: August 30, 2005
FILED: July 29, 2002
APPLICATION NUMBER: 208636
ABSTRACT:
A power amplifier circuit whose performance is optimized by operating its stages in substantially close to a Class B mode by reducing quiescent current during low driver signal levels. As the driver signal amplitude increases, the operation of the amplifier is configured to dynamically adjust to be in a Class AB mode, thereby increasing the power efficiency of the overall circuit at kiw drive levels. A further enhancement to the power amplifier circuit includes a temperature compensation circuit to adjust the bias of the amplifier so as to stabilize the performance in a wide temperature range.
Patent No. 6882227: Bias Circuit Linearization and Dynamic Power Control
ISSUED: April 19, 2005
FILED: September 15, 2003
APPLICATION NUMBER: 662849
ABSTRACT:
A transistor bias circuit is provided that is capable of biasing an amplifier transistor having a control terminal, a current-sink terminal, and a current-source terminal in order to control inter-modulation and linearize the output corresponding to radio frequency and microwave frequency ranges. Additionally, an embodiment of the present circuit is capable of dynamic power control. The transistor bias circuit according to the present invention utilizes a leakage current to alter the electrical characteristics of the amplifier transistor. The bias circuit comprises a bias transistor having a control terminal, a current-sink terminal, and a current-source terminal. Additionally, at least one DC input port, at least one resonator element, a diode element, and a resistive element is provided.
Patent No. 6856004: Compact layout for a semiconductor device
ISSUED: February 15, 2005
FILED: December 19, 2002
APPLICATION NUMBER: 327512
ABSTRACT:
A semiconductor device includes a semiconductor substrate, an electrode disposed on an upper surface of the substrate, and a set of one or more transistor element(s) disposed on the upper surface of the substrate. The set of transistor element(s) compactly surrounds the electrode with a threshold distance. In one embodiment, the set also compactly surrounds a via hole. In another, the element(s) comprises a bipolar junction transistor that has an aggregate emitter length of not less than 10 microns. In still another embodiment, the device is coupled to a RF circuit for power amplification.
Patent No. 6853526: Transient Overvoltage Protection Circuit
ISSUED: February 8, 2005
FILED: September 22, 2000
APPLICATION NUMBER: 668181
ABSTRACT:
A circuit and method are disclosed for protecting an integrated circuit (IC) against transient overvoltages. The circuit comprises a balun transformer and a normally-off transistor. The balun input terminals are connected to an unbalanced circuit, while the balun output terminals are connected to a balanced circuit. The transistor is connected between the balun output terminals and has a gate connected to ground or to some other reference voltage. When an overvoltage transient signal reaches the balun input terminals, the balun transformer converts the transient to a balanced transient signal on the two branches of the balanced circuit. During overvoltage conditions, one balun output terminal will have a voltage which swings low enough that the protection transistor turns on, effectively shorting the overvoltage spike and protecting any upstream (or downstream) IC components from damage. When the transient is over, the transistor returns to the "off" state.
Patent No. 6842075: Gain Block with Stable Internal Bias from Low-voltage Power Supply
ISSUED: January 11, 2005
FILED: December 13, 2002
APPLICATION NUMBER: 319921
ABSTRACT:
A transistor bias circuit is provided that is capable of operating from a power supply voltage that is slightly higher than twice the base-emitter voltage of the transistor to be biased. The bias circuit includes a transistor connected in a current-mirror configuration with the transistor to be biased. A feedback circuit maintains the mirrored current at a constant level. The gain of the feedback circuit is improved by the addition of a non-inverting amplifier within the feedback circuit. In a preferred embodiment, the biased transistor is concurrently in both a Darlington and the current mirror configuration. Moreover, a feedback transistor in the feedback circuit is also concurrently in the Darlington configuration, thus providing an efficient biasing arrangement for an amplifier block based on the Darlington arrangement.
Patent No. 6806767: Power Amplifier with Load Switching Circuit
ISSUED: October 19, 2004
FILED: July 9, 2002
APPLICATION NUMBER: 190567
ABSTRACT:
A power amplifier circuit includes a power amplifier responsive to a power mode signal, the power amplifier having a power amplifier output node, and a power amplifier load circuit also responsive to the power mode signal, the power amplifier load circuit having a load circuit input node connected to the power amplifier output node. The power amplifier load circuit has a first transmission line coupled between the load circuit input node and a first node, a harmonic filter coupled between the load circuit input node and a common node, a first capacitor coupled between the first node and the common node, and a first switch coupled between the common node and ground, where the first switch is responsive to the power mode signal.
Patent No. 6803824: Dynamic Matching in Cascode Circuits
ISSUED: October 12, 2004
FILED: December 18, 2001
APPLICATION NUMBER: 024943
ABSTRACT:
A method and apparatus for a variable gain cascode amplifier (or attenuator) is disclosed. Embodiments provide for a compensated input impedance. A gain/impedance controller compensates input impedance corresponding to gain adjustments.
Patent No. 6760900: Integrated circuits with scalable design
ISSUED: July 6, 2004
FILED: December 3, 2001
APPLICATION NUMBER: 004976
ABSTRACT:
A method for designing at least one mask for manufacturing an integrated circuit is disclosed. The method may include generating a schematic; entering data representing transistors of the set into a computer-aided design system; identifying transistors expected to be subject to voltage levels beyond the bounds of a power rail and a ground rail; designating robust geometries such transistors and operating the computer-aided design system to generate mask or masks. Integrated circuits of scalable design are also disclosed.
Patent No. 6759922: High directivity multi-band coupled-line coupler for RF power amplifier
ISSUED: July 6, 2004
FILED: May 20, 2002
APPLICATION NUMBER: 147987
ABSTRACT:
The present invention discloses a miniature high directivity multi-band coupled-line coupler for RF power amplifier module application. The coupler utilizes a three-coupled-line structure, with a first RF line designated coupled line for the GSM 900 MHZ band, a second RF line designated coupled line for the DCS/PCS 1800/1900 MHZ band, and a common coupled line. A first capacitor is connected between the center of the first line and the center of the common line and a second capacitor is connected between the center of the second line and the center of the common line. The coupler has a length considerably less than the length of a quarter wave length coupler while achieving directivity requirements for both GSM band and DCS/PCS band.
Patent No. 6753734: Multi-mode amplifier bias circuit
ISSUED: June 22, 2004
FILED: February 4, 2003
APPLICATION NUMBER: 358371
ABSTRACT:
There is disclosed a bias circuit exhibiting good stability over variations in temperature and power supply voltage and capable of generating a plurality of discrete levels of output current for biasing RF power amplifier. In accordance with the invention, the bias circuit includes (1) a master transistor connected to the slave transistor in a current-mirror configuration and having two parallel-connected transistor elements, (2) a switch connected to at least one transistor element to control its operation, and (3) a feedback circuit by which the voltage at the collector of the master transistor may be fed back to control the voltages at the bases of the master transistor and the slave transistor. Moreover, the bias circuit can be operated from a power supply voltage that is just above twice the value of the base-emitter voltage of the transistor in the circuit.
Patent No. 6724067: Low stress thermal and electrical interconnects for heterojunction bipolar transistors
ISSUED: April 20, 2004
FILED: October 7, 2002
APPLICATION NUMBER: 265548
ABSTRACT:
A thermal and electrical interconnect for heterojunction bipolar transistors is disclosed wherein the interconnect is essentially comprised of gold and in thermal and electrical contact with each of the interdigitated emitter fingers and is capable of transporting heat fluxes between 0.25-1.5 mW/.mu.m2. The interconnect is electrodeposited to form a low-stress interface with the emitter finger, thereby increasing the lifetime and reliability of the transistor.
Patent No. 6719518: Portable tube holder apparatus
ISSUED: April 13, 2004
FILED: October 15, 2001
APPLICATION NUMBER: 977740
ABSTRACT:
A portable tube holder apparatus and tube loading method facilitates safe and rapid loading of tubes containing electronic components into a machine. The tube holder has a tube guide sized to receive a plurality of tubes and a support to selectively hold the tubes in that guide. The holder can be loaded with a relatively large number of tubes at a workstation area and then used to safely transport the tubes to the machine without risk of the components falling out of the tubes. The support, which is preferably slidable, permits all of the tubes in the guide to be readily released into the machine's feeding system, enabling fast loading of the machine and also minimizing down-time for machines that cannot run while being loaded. The portable tube holder preferably has an interface designed to facilitate alignment of the tube holder's guide with the feeding system guide in the machine.
Patent No. 6710657: Gain control circuit with well-defined gain states
ISSUED: March 23, 2004
FILED: October 12, 2001
APPLICATION NUMBER: 975849
ABSTRACT:
A current steering-type gain control circuit provides a non-zero minimum gain in response to readily reproducible control signal conditions and without requiring sophisticated control-signal-generating circuitry. The gain control circuit is adapted from a conventional differential pair of current-steering transistors, biased by first and second control signals respectively. To provide a well-defined non-zero minimum gain, the gain control circuit includes at least one additional current steering transistor that further steers current to the output when conducting in the minimum gain state. By further including one or more additional pairs of current steering transistors, the gain control circuit also provides a plurality of well-defined states with gains between the maximum and minimum gain values of the circuit. The minimum and intermediate gain values, may be selected by varying the physical characteristics of the current steering transistors which may be BJTs or FETs. The circuit may be implemented in a single-ended or differential configuration.
Patent No. 6664500: Laser-trimmable digital resistor
ISSUED: December 16, 2003
FILED: December 16, 2000
APPLICATION NUMBER: 737699
ABSTRACT:
A laser system and method for cleanly trimming or severing resistive links fabricated on in undoped gallium arsenide substrate without damaging or affecting adjacent circuit structures or the underlying or surrounding substrate is disclosed. The system includes a laser source adapted to generate an output at a wavelength within the range of 0.9 to 1.5 .mu.m, a resistive film structure formed on an undoped gallium arsenide substrate, and a beam positioner and alignment system to align the laser source with the target structure. The method includes generating a laser output at a wavelength in a range of about 0.9 to 1.5 .mu.m and directing the laser output to illuminate a resistive thin-film structure fabricated on a gallium arsenide substrate. The resistive film structure includes a first layer of protective dielectric and a layer of resistive thin-film material. Preferably, a second layer of protective dielectric lies upon the layer of resistive thin-film material. Further, there is disclosed a resistive trim network suitable for use with a bias circuit for a power amplifier that requires a quiescent current of 130 mA. The trim network includes eleven thin-film resistors arranged in an asymmetrical array of series resistors, parallel resistors, and tying resistors.
Patent No. 6645790: System and Method for Prototyping and Fabricating Complex Microwave Circuits
ISSUED: November 11, 2003
FILED: December 21, 2001
APPLICATION NUMBER: 032321
ABSTRACT:
The present invention is generally drawn to a system and method for creating RF integrated microwave circuits that can support multiple applications where many RF functions can be derived from a generic integrated circuit after the RF integrated microwave circuit is manufactured. More specifically, the present invention can provide active and passive device building blocks of respective monolithic microwave integrated circuit (MMIC) arrays and substrates that can be coupled together in various ways after manufacture of the integrated circuits to achieve multiple applications. This can accomplished by manufacturing chips with multiple active device blocks that can support various and multiple applications and that can be coupled together in various ways, adjusted, or tuned after manufacture.
Patent No. 6642578: Improved Linearity Radio Frequency Switch with Low Control Voltage
ISSUED: November 4, 2003
FILED: July 22, 2002
APPLICATION NUMBER: 201494
ABSTRACT:
A field effect transistor used in radio frequency switching applications and having a linear performance characteristic is disclosed. The transistor comprises a plurality of gate lines, a source terminal, a drain terminal, and two feed forward capacitors electrically coupled to the source and drain terminals and the gate line at a plurality of points along the line. An improved transistor preferably includes three or more gate lines to help improve harmonic suppression.
Patent No. 6639466: Amplifier bias adjustment circuit to maintain high-output third-order intermodulation distortion performance
ISSUED: October 28, 2003
FILED: June 11, 2002
APPLICATION NUMBER: 167604
ABSTRACT:
An circuit and method are provided for amplifying RF input signal to produce RF output signals with third-order intermodulation distortion products. The circuit and method use a feedback signal to control the bias voltage of the amplifier, such that the output third-order intermodulation distortion product increases monotonically with the RF input signal power. Specifically, the third-order intermodulation distortion product responds over a predetermined output power range by increasing three decibels in response to each one-decibel increase in input power.
Patent No. 6580321: Active clamping circuit for power amplifier
ISSUED: June 17, 2003
FILED: August 24, 2001
APPLICATION NUMBER: 939183
ABSTRACT:
An active clamping circuit for a multi-stage power amplifier includes a feedback circuit which affects the gain of the amplifier. The feedback circuit feeds an output via a filter and a clamping transistor to an input of at least one stage of the power amplifier. The output fed to the filter and clamping transistor may be tapped from one or more diodes belonging to a diode stack connected to the power amplifier's output.
Patent No. 6577198: Active power splitter with impedance matching
ISSUED: June 10, 2003
FILED: March 21, 2002
APPLICATION NUMBER: 101775
ABSTRACT:
A single-input/multiple output power splitter having internal feedback circuitry. A separate amplifying circuit, such as a transistor, is used to drive each of the outputs. The transistors may be arranged in a common source/emitter amplifying configuration in which the gates/bases are connected together as an input node. Each transistor has an associated feedback circuit including passive circuit elements, such as resistors. The passive circuit elements are connected between the drain/collector of its corresponding transistor and a common intermediate connecting node to which all feedback resistors are also connected. The common intermediate node is connected to the single input via a separate input resistor.
Patent No. 6559722: Low bias current/temperature compensation current mirror for linear power amplifier
ISSUED: May 6, 2003
FILED: August 8, 2000
APPLICATION NUMBER: 634628
ABSTRACT:
A power amplifier circuit is disclosed, whose power efficiency is optimized by operating its stages in substantially close to a Class B mode by reducing the quiescent current during low driver signal levels. As the driver signal amplitude increases, the amplifier is dynamically biased to operate in a Class AB mode. A further enhancement to the power amplifier circuit includes a temperature compensation circuit to adjust the bias of the amplifier so as to stabilize the performance over a wide temperature range.
Patent No. 6554949: Wafer demount receptable for separation of thinned wafer from mounting carrier
ISSUED: April 29, 2003
FILED: September 17, 2002
APPLICATION NUMBER: 244548
ABSTRACT:
A wafer demounting receptacle comprises a substantially circular plate member and an upstanding rim structure provided around a periphery of the plate member. The rim structure is stepped and includes a first step defining a first diameter, and a second step defining a second diameter grater than the first diameter. The riser of the first step has a very low height so that a gap between the plate member and a fragile semiconductor wafer bonded to a carrier having a peripheral abutment surface resting on the run of the first step, limits the bending of an edge portion of the wafer in a direction towards the plate member while the wafer is partially demounted from a wafer carrier. The plate member is further provided with a pattern of holes that generates eddy currents in a solvent that flows over the wafer, carrier, and receptacle so as to soften and dissolve the mounting adhesive between the wafer and carrier such that the wafer is separated from the carrier. The wafer demount receptacle can be used in conjunction with a wafer demount tool comprising a chamber defined between a backing plate and a contact plate. The chamber is provided with a gas inlet for introducing a pressurized gas, while the contact plate is provided with a plurality of through-holes. The wafer demount tool is mated to the wafer demount receptacle such that the contact plate is juxtaposed against the back side of a wafer carrier resting in the wafer demount receptacle. Pressurized gas flowing through the wafer demount tool displaces solvent from the wafer-carrier interface to further promote separation of the wafer from the carrier.
Patent No. 6515546: Bias circuit for use with low-voltage power supply
ISSUED: February 4, 2003
FILED: June 6, 2001
APPLICATION NUMBER: 875117
ABSTRACT:
A transistor bias circuit is provided that is capable of operating from a power supply voltage that is slightly higher than twice the base-emitter voltage of the transistor to be biased. The bias circuit includes a transistor connected in a current-mirror configuration with the transistor to be biased. A feedback circuit maintains die mirrored current at a constant level. The gain of the feedback circuit is improved by the addition of a non-inverting amplifier within the feedback circuit.
Patent No. 6501331: Multi-band amplifier
ISSUED: December 31, 2002
FILED: March 29, 2001
APPLICATION NUMBER: 821177
ABSTRACT:
A GaAs MMIC dual-band amplifier for wireless communications is disclosed for operation at either the 800 MHz or the 1900 MHz band and it provides desired gain and input and output impedance. Switching impedance networks are used at the input and output of the amplifier to provide matching input impedance and desired output impedance for operation in the two bands. Switching impedance networks are also used between any successive stages of the amplifier to provide proper interstage impedance. The dual band amplifier includes a bias control circuit which biases the amplifier to operate in A, B, AB or C mode. The amplifier can be used for the AMPS 800 or the GSM 900 operation or any other cellular operation such as the PCS 1900 and it can be switched between the two operations by simply applying a proper control signal to the amplifier.
Patent No. 6491083: Wafer demount receptacle for separation of thinned wafer from mounting carrier
ISSUED: December 10, 2002
FILED: February 6, 2001
APPLICATION NUMBER: 776758
ABSTRACT:
A wafer demounting receptacle comprises a substantially circular plate member and an upstanding rim structure provided around a periphery of the plate member. The rim structure is stepped and includes a first step defining a first diameter, and a second step defining a second diameter grater than the first diameter. The riser of the first step has a very low height so that a gap between the plate member and a fragile semiconductor wafer bonded to a carrier having a peripheral abutment surface resting on the run of the first step, limits the bending of an edge portion of the wafer in a direction towards the plate member while the wafer is partially demounted from a wafer carrier. The plate member is further provided with a pattern of holes that generates eddy currents in a solvent that flows over the wafer, carrier, and receptacle so as to soften and dissolve the mounting adhesive between the wafer and carrier such that the wafer is separated from the carrier. The wafer demount receptacle can be used in conjunction with a wafer demount tool comprising a chamber defined between a backing plate and a contact plate. The chamber is provided with a gas inlet for introducing a pressurized gas, while the contact plate is provided with a plurality of through-holes. The wafer demount tool is mated to the wafer demount receptacle such that the contact plate is juxtaposed against the back side of a wafer carrier resting in the wafer demount receptacle. Pressurized gas flowing through the wafer demount tool displaces solvent from the wafer-carrier interface to further promote separation of the wafer from the carrier.
Patent No. 6470946: Wafer demount gas distribution tool
ISSUED: October 29, 2002
FILED: February 6, 2002
APPLICATION NUMBER: 776922
ABSTRACT:
A wafer demounting receptacle comprises a substantially circular plate member and an upstanding rim structure provided around a periphery of the plate member. The rim structure is stepped and includes a first step defining a first diameter, and a second step defining a second diameter grater than the first diameter. The riser of the first step has a very low height so that a gap between the plate member and a fragile semiconductor wafer bonded to a carrier having a peripheral abutment surface resting on the run of the first step, limits the bending of an edge portion of the wafer in a direction towards the plate member while the wafer is partially demounted from a wafer carrier. The plate member is further provided with a pattern of holes that generates eddy currents in a solvent that flows over the wafer, carrier, and receptacle so as to soften and dissolve the mounting adhesive between the wafer and carrier such that the wafer is separated from the carrier. The wafer demount receptacle can be used in conjunction with a wafer demount tool comprising a chamber defined between a backing plate and a contact plate. The chamber is provided with a gas inlet for introducing a pressurized gas, while the contact plate is provided with a plurality of through-holes. The wafer demount tool is mated to the wafer demount receptacle such that the contact plate is juxtaposed against the back side of a wafer carrier resting in the wafer demount receptacle. Pressurized gas flowing through the wafer demount tool displaces solvent from the wafer-carrier interface to further promote separation of the wafer from the carrier.
Patent No. 6458640: GaAs MESFET having LDD and non-uniform P-well doping profiles
ISSUED: October 1, 2002
FILED: June 4, 2001
APPLICATION NUMBER: 871740
ABSTRACT:
A MESFET has a conduction channel provided with a first doping profile in a first portion which extends between the source and the gate, and a second doping profile in a second portion which extends between the gate and the drain. A background p-type region is provided beneath the first portion, but not necessarily behind the second portion.
Patent No. 6437585: Electrical contactor for automatic testing of chips including RF chips
ISSUED: August 20, 2002
FILED: October 27, 2000
APPLICATION NUMBER: 699179
ABSTRACT:
An electrical contactor for establishing an electrical contact between a chip and a printed circuit board for testing chips comprising a conductive layer and a ground contact pedestal. The ground contact pedestal is preferably press fit and soldered onto a ground layer of the printed circuit board for establishing good ground contact with the chip. In addition, the contactor preferably has a thin profile that does not electrically interfere with sensitive electronics contained within the chip. The contactor also does not use a plastic frame for mounting purposes. Such plastic frames reduce accessibility to the printed circuit board, making fine tuning electronics in the printed circuit board more difficult. Rather, the contactor preferably includes two holes in its conductive layer that mount on dowels in the printed circuit board and is secured to the dowels by two O-rings.
Patent No. 6415843: Spatula for separation of thinned wafer from mounting carrier
ISSUED: July 9, 2002
FILED: January 10, 2001
APPLICATION NUMBER: 756849
ABSTRACT:
A wafer removing spatula has a handle connected to a tray. A shaft of the handle is provided with a pair of support guides and the tray is provided with a wafer support surface which rests on a tray support surface. The support guides and the tray support surface are configured and dimensioned to ensure that the wafer support surface is substantially parallel to the upper surface of a base plate on which both the support guides and the tray support surface rest. A front edge of the wafer support surface is provided with a bevel to facilitate lifting a wafer from a wafer carrier surface. The height of the lowermost portion of the front edge is approximately the same as the height of a wafer carrier placed on the base plate. During operation, the spatula is moved on the base plate towards the carrier with the wafer mounted thereon. The front edge of the spatula eases just above the upper surface of the wafer carrier such that the beveled edge creates and then enters a separation gap between the wafer and the wafer carrier, thereby causing the wafer to separate from the wafer carrier and climb onto the wafer support surface.
Patent No. 6404284: Amplifier bias adjustment circuit to maintain high-output third-order intermodulation distortion performance
ISSUED: June 11, 2002
FILED: April 19, 2001
APPLICATION NUMBER: 837987
ABSTRACT:
An circuit and method are provided for amplifying RF input signal to produce RF output signals with third-order intermodulation distortion products. The circuit and method use a feedback signal to control the bias voltage of the amplifier, such that the output third-order intermodulation distortion product increases monotonically with the RF input signal power. Specifically, the third-order intermodulation distortion product responds over a predetermined output power range by increasing three decibels in response to each one-decibel increase in input power.
Patent No. 6314008: Adjustable low spurious signal DC-DC converter
ISSUED: November 6, 2001
FILED: October 16, 2000
APPLICATION NUMBER: US2000000688548
ABSTRACT:
The present invention uses an AC signal and an external DC control voltage to generate a plurality of levels of output DC voltages. The level of the output voltage is determined by the DC control voltage and has the opposite polarity. The invention is preferably implemented as a balanced circuit, which generates spurious signals at even harmonics of the AC frequency signal. The spurious signals can then be filtered out using a low-pass filter.
Related press release
Patent No. 6242986: Multiple-band amplifier
ISSUED: June 5, 2001
FILED: May 18, 1998
SERIAL NUMBER: 080786
ABSTRACT:
A GaAs MMIC dual-band amplifier for wireless communications is disclosed for operation at either the 800 MHz or the 1900 MHz band and it provides desired gain and input and output impedance. Switching impedance networks are used at the input and output of the amplifier to provide matching input impedance and desired output impedance for operation in the two bands. Switching impedance networks are also used between any successive stages of the amplifier to provide proper interstage impedance. The dual band amplifier includes a bias control circuit which biases the amplifier to operate in A, B, AB or C mode. The amplifier can be used for the AMPS 800 or the GSM 900 operation or any other cellular operation such as the PCS 1900 and the it can be switched between the two operations by simply applying a proper control signal to the amplifier.
Related press release
Patent No. 6005375: Amplifier using a single polarity power supply
ISSUED: Dec. 21, 1999
FILED: May 5, 1998
SERIAL NUMBER: 072860
ABSTRACT:
The present invention provides a power amplifier operating with a single power supply. The amplifier includes at least one depletion-mode FET for amplifying an ac signal and a negative voltage generator for providing a bias to the FET. Preferably the amplifier further includes a negative voltage regulator to provide a regulated bias to bias the FET for a class A, AB or B operation. The negative generator includes a multivibrator for producing two clock signals and a charge pump which receives the clock signals and produces a negative voltage. Advantageously the negative voltage is provided as a low reference potential to the multivibrator so that the clock signals it produced include a negative voltage period, which enables the charge pump to operate in a power efficient manner.
Related press release
Patent Number 5952860: Amplifier using a single polarity power supply
ISSUED: Sep. 14, 1999
FILED: May 5, 1998
SERIAL NUMBER: 072865
ABSTRACT:
The present invention provides a power amplifier operating with a single power supply. The amplifier includes at least one depletion-mode FET for amplifying an ac signal and a negative voltage generator for providing a bias to the FET. Preferably the amplifier further includes a negative voltage regulator to provide a regulated bias to bias the FET for a class A, AB or B operation. The negative generator includes a multivibrator for producing two clock signals and a charge pump which receives the clock signals and produces a negative voltage. Advantageously the negative voltage is provided as a low reference potential to the multivibrator so that the clock signals it produced include a negative voltage period, which enables the charge pump to operate in a power efficient manner.
Related press release
Patent Number 5892400: Amplifier using a single polarity power supply and including depletion mode FET and negative voltage generator
ISSUED: Apr. 6, 1999
FILED: Dec.12, 1996
SERIAL NUMBER: 764350
ABSTRACT:
The present invention provides a power amplifier operating with a single power supply. The amplifier includes at least one depletion-mode FET for amplifying an ac signal and a negative voltage generator for providing a bias to the FET. Preferably the amplifier further includes a negative voltage regulator to provide a regulated bias to bias the FET for a class A, AB or B operation. The negative generator includes a multivibrator for producing two clock signals and a charge pump which receives the clock signals and produces a negative voltage. Advantageously the negative voltage is provided as a low reference potential to the multivibrator so that the clock signals it produced include a negative voltage period, which enables the charge pump to operate in a power efficient manner.
Related press release
Patent Number 5774017: Multiple-band amplifier
ISSUED: Jun. 30, 1998
FILED: Jun. 3, 1996
SERIAL NUMBER: 664972
ABSTRACT:
A GaAs MMIC dual-band amplifier for wireless communications is disclosed for operation at either the 800 MHz or the 1900 MHz band and it provides desired gain and input and output impedance. Switching impedance networks are used at the input and output of the amplifier to provide matching input impedance and desired output impedance for operation in the two bands. Switching impedance networks are also used between any successive stages of the amplifier to provide proper interstage impedance. The dual band amplifier includes a bias control circuit which biases the amplifier to operate in A, B, AB or C mode. The amplifier can be used for the AMPS 800 or the GSM 900 operation or any other cellular operation such as the PCS 1900 and the it can be switched between the two operations by simply applying a proper control signal to the amplifier.
Related press release
Patent Number 5748049: Multiple-band amplifier
ISSUED: May 5, 1998
FILED: Nov. 23, 1994
SERIAL NUMBER: 344753
ABSTRACT:
A multiple-frequency local oscillator for providing an LO signal at one of a multiple of predetermined resonant frequencies associated with a number of resonators is disclosed. It includes a number of LO input ports for coupling to a plurality of resonators, respectively, each resonator having a predetermined resonant frequency; the local oscillator is controlled to selectively provide at its LO output port an output LO signal at any one of the resonant frequencies.
Patent Number 5736913: Method and apparatus for providing grounding to microwave circuit by low impedance means
ISSUED: Apr. 7, 1998
FILED: Feb. 14, 1996
SERIAL NUMBER: 601499
ABSTRACT:
An electrical circuit forming a dual-channel low current Low Noise Low impedance means are provided for coupling a common circuit ground of a microwave circuit to the ground potential. The low impedance means include a plurality of resonators, each having a distinct resonant frequency at which it displays a minimum impedance. The resonant frequencies of the resonators are chosen and arranged such that the resonators together operate to provide a low impedance band in the frequency spectrum within which low impedance coupling between the common circuit ground and the ground potential is achieved. In a preferred embodiment, resonators include capacitors connected in series with inductive bonding wires, and different resonant frequencies are obtained by using capacitors with different capacitance.
Related press release
Patent Number 5659894: Dual-channel low current low noise block downconverter
ISSUED: Aug. 19, 1997
FILED: Sep. 26, 1995
SERIAL NUMBER: 533796
ABSTRACT:
An electrical circuit forming a dual-channel low current Low Noise Block (LNB) downconverter comprising two downconverting circuits electrically connected in series with each other and each electrically connected in parallel with a Zener diode such that power consumption is minimized and component life improved.
Related press release
Patent Number 5646573: Automatic gain-control transimpedance amplifier
ISSUED: Jul. 8 , 1997
FILED: Feb. 28, 1995
SERIAL NUMBER: 395775
ABSTRACT:
Automatic Gain Transimpedance Amplifiers for analog applications having high bandwidth, wide dynamic range, and ultra-high linearity. The transimpedance amplifiers includes an operational amplifier and a variable feedback resistance means connected between the input and the output of the amplifier. The variable feedback resistance means may include a single feedback PIN diode, two serially connected feedback PIN didoes, a PIN diode connected to a feedback resistor in parallel, or two serially connected PIN diodes connected to a feedback resistor in parallel. Ultra-high linearity is achieved because the dynamic resistance of the PIN diode under forward bias is substantially linearly dependent on the inverse of the current that passes the diode.
Related press release
Patent Number 5625307: Low cost monolithic gallium arsenide upconverter chip
ISSUED: Apr. 29, 1997
FILED: Mar. 3, 1992
SERIAL NUMBER: 845293
ABSTRACT:
A monolithic upconverter integrated circuit is described which performs the first frequency conversion of a dual conversion cable television (CATV) receiver. The upconverter chip includes three functional blocks: a Gilbert type image-rejecting mixer, a phase splitter, and a voltage-controlled oscillator. Mixing is performed by a novel Gilbert type mixer including image-rejection inductors to improve the noise figure of the mixer. A differential circuit topology allows the monolithic upconverter chip to utilize a plastic dual inline batwing package without considerable performance loss. On-chip RF bypass networks, in the form of series RC terminations, also help compensate for the undesirable effects of pin inductances in the dual inline package. A resistor-based DC biasing scheme dramatically reduces power-up latency, allowing faster testing.
Related press release
Patent Number 5602510: Automatic transimpedance control amplifier having a variable impedance feedback
ISSUED: Feb. 11, 1997
FILED: Jun. 8, 1995
SERIAL NUMBER: 406279
ABSTRACT:
An automatic transimpedance control amplifier is disclosed. The amplifier incorporates an automatic gain control circuit which simultaneously and automatically adjust the value of transimpedance and the voltage gain at each gain stage of the amplifier according to the input current. The amplifier has wide bandwidth, high sensitivity/and more importantly, wide dynamic range.
Related press release
Patent Number 5563545: Low cost monolithic GaAs upconverter chip
ISSUED: Oct. 8 , 1996
FILED: Sep. 27, 1994
SERIAL NUMBER: 312730
ABSTRACT:
A monolithic upconverter integrated circuit is described which performs the first frequency conversion of a dual conversion cable television (CATV) receiver.
The upconverter chip includes three functional blocks: a Gilbert type image-rejecting mixer, a phase splitter, and a voltage-controlled oscillator. Mixing is performed by a novel Gilbert type mixer including image-rejection inductors to improve the noise figure of the mixer. A differential circuit topology allows the monolithic upconverter chip to utilize a plastic dual inline batwing package without considerable performance loss. On-chip RF bypass networks, in the form of series RC terminations, also help compensate for the undesirable effects of pin inductances in the dual inline package. A resistor-based DC biasing scheme dramatically reduces power-up latency, allowing faster testing.
Patent Number 5557144: Plastic packages for microwave frequency applications
ISSUED: Sep. 17, 1996
FILED: Jan. 29, 1993
SERIAL NUMBER: 01073
ABSTRACT:
A plastic package for microwave applications up to 14 GHz is disclosed. The plastic package includes a plastic platform, a lead frame embedded on the surface of the platform and, in one embodiment, a plastic cap mounted on the platform so as to seal the chip within the package.
The lead frame includes a baseplate for mounting at least one semiconductor chip, at least one ground lead attached to the baseplate and extending outwardly therefrom, and at least one signal lead for conducting signals to or from such semiconductor chip. The signal lead and at least one ground lead are configured as a microwave transmission line such as microwave coplanar strips, or microwave coplanar waveguide for transmitting microwave frequency signals. The package offers a low inductance ground path, good thermal characteristics, and low parasitic inductance and capacitance. It can be applied for high speed and high frequency applications.
Patent Number 5493718: Dual-channel low current low noise block downconverter
ISSUED: Feb. 20, 1996
FILED: Aug. 26, 1993
SERIAL NUMBER: 112778
ABSTRACT:
An electrical circuit forming a dual-channel low current Low Noise Block (LNB) downconverter comprising two downconverting circuits electrically connected in series with each other and each electrically connected in parallel with a Zener diode such that power consumption is minimised and component life improved.
Patent Number 5442321: Automatic transimpedance control amplifier
ISSUED: Aug. 15, 1995
FILED: July 8, 1993
SERIAL NUMBER: 089201
ABSTRACT:
An automatic transimpedance control amplifier is disclosed. The amplifier incorporates an automatic gain control circuit which simultaneously and automatically adjust the value of transimpedance and the voltage gain at each gain stage of the amplifier according to the input current. The amplifier has wide bandwidth, high sensitivity, and more importantly, wide dynamic range.
Patent Number 5428837: Method and apparatus for reducing local oscillator leakage in integrated circuit receivers
ISSUED: June 27, 1995
FILED: Jan 13, 1993
SERIAL NUMBER: 003897
ABSTRACT:
Technique for reducing local oscillator leakage in integrated frequency conversion circuits is disclosed, which provides coupling an external portion of a resonator circuit to the integrated frequency conversion circuit. The coupling is accomplished without using any of the DC power or ground pins of the conversion circuit. A frequency conversion circuit based on this technique includes resonator, oscillator, and mixer circuits. Part of the oscillator and mixer circuit is encapsulated in a package, whereas at least a portion of the resonator circuit is located outside the package. The outside portion of the resonator circuit connects to at least two external resonator pins of the package such that, during the operating of the conversion circuit, the net current entering the package via said external resonator pins is approximately zero.
Congratulations ANADIGICS’ engineers for their Patents in 2009!
KEN OZARD (2 Patents) – ESD protection device and Device and method for PA noise reduction
JULIO REYES’ - System and method for improving power efficiency in GSM PAs
HENRY LIWINSKI’s - Voltage regulated power supply system both were granted patents
JOHN BAYRUNS - Tunable balanced loss compensation in an electronic filter
